Semicon 2.0 Explained: How India Plans to Build Its Own Chip Design and Semiconductor Ecosystem

• Second phase of India's semiconductor strategy: Semicon 2.0 is the expanded national programme intended to create capabilities across the entire semiconductor value chain rather than merely subsidising fabrication facilities.

• The first Semicon India Programme was launched in 2021 as India sought to attract semiconductor fabrication, packaging and chip-design investment. Semicon 2.0 builds on that foundation but places greater emphasis on technological depth, indigenous intellectual property, critical equipment, materials, research and skilled manpower.

• Strategic purpose: The government describes semiconductors as important not only for economic growth but also for national security and supply-chain resilience. Chips are embedded in telecommunications, automobiles, power electronics, defence systems, artificial intelligence, medical devices, satellites, industrial machinery and digital infrastructure.

• Foundation of modern electronics: A semiconductor is a material whose electrical conductivity lies between that of a conductor and an insulator. Its electrical properties can be controlled, allowing engineers to create transistors, diodes and integrated circuits.

• Billions of tiny transistors can be placed on a semiconductor chip to perform calculation, memory, sensing, communication and power-management functions.

• Economic importance: Electronics, EVs, telecom equipment, data centres, AI systems and industrial automation increasingly depend on sophisticated chips.

• National-security dimension: Defence platforms, radar, communications, satellites, drones, missiles, electronic warfare systems and secure networks also depend on trusted semiconductor supplies.

• NITI Aayog therefore describes semiconductor capability as increasingly connected with economic competitiveness, technological sovereignty and strategic autonomy.

• India's paradox: India is already a major global location for semiconductor engineering and design centres operated by multinational companies. NITI Aayog estimates that the country accounts for roughly one-fifth of the global semiconductor design workforce.

• But having engineers working in India is not the same as having Indian companies own the final chip architecture, intellectual property and product.

• A multinational company may employ thousands of engineers in Bengaluru, Hyderabad or Noida, yet the chip's commercial IP, brand, strategic decisions and revenue may still belong to the foreign parent company.

• Central policy gap: India therefore wants to move from being primarily a provider of design talent to becoming a creator and owner of semiconductor IP.

• This is the core reason design receives such prominence in Semicon 2.0.

• Intellectual property: Semiconductor IP refers to reusable designs, architectures or functional blocks used in creating chips.

• Examples can include processor cores, memory controllers, communication interfaces, security blocks, radio-frequency components and digital-signal-processing modules.

• Why IP matters: Semiconductor value is not determined only by the factory that fabricates the chip. Much of the strategic and commercial value lies in the architecture and intellectual property defining what the chip does.

• Owning semiconductor IP therefore provides: technological control;

licensing revenue; product differentiation; greater bargaining power in global supply chains; and reduced dependence on foreign technology providers.

• Design: Engineers decide what the chip should do and create its electronic architecture.

• Fabrication: The design is physically manufactured on a silicon or other semiconductor wafer inside a highly specialised fabrication plant or “fab”.

• Assembly and packaging: Individual chips cut from the wafer are packaged so that they can be incorporated into electronic systems.

• Testing: Chips are tested for performance, reliability and defects.

• Equipment and materials: All these stages depend upon sophisticated lithography systems, deposition and etching machines, ultrapure chemicals, gases, wafers, photomasks and substrates.

• Thus, a country can participate in the semiconductor industry at many points without performing every stage domestically.

• Fabless model: A fabless semiconductor company designs and markets chips but does not own the expensive factory that physically manufactures them.

• It sends the final design to a specialised semiconductor foundry.

• Major parts of the global semiconductor industry work through this division of labour.

• Why important for India: Building a leading-edge semiconductor fab may require enormous capital investment, specialised infrastructure and long gestation periods. A fabless company can enter the semiconductor market with significantly lower capital requirements.

• For India, which already possesses deep design talent, building globally competitive fabless companies can therefore be a faster route towards semiconductor IP ownership.

• The design pillar has three separate objectives.

• Strategic semiconductor design: The first category focuses on semiconductor IP, chips, SoCs and modules required for national importance and strategic priorities.

• Commercial semiconductor design: The second category supports Indian companies seeking to develop chips that can compete in commercial markets.

• Deployment-linked support: The third category assists newly designed chips after product development by helping them achieve commercial deployment and customer adoption.

• The separation is significant because creating a strategic defence chip, building a commercially profitable chip start-up and getting an already-developed product accepted by manufacturers involve different policy problems.

• Government identifies priorities: Strategic semiconductor technologies may include building blocks in compute, memory, radio frequency, power electronics, networking and sensors.

• C-DAC's role: The Centre for Development of Advanced Computing can invite proposals and provide technical infrastructure and financial support.

• Indian control: Strategic-category companies face strict Indian incorporation, headquarters, ownership and operational-presence requirements.

• IP arrangement: Under the operational framework described in the notified scheme, intellectual property developed through this route may be jointly held by the selected company and C-DAC, although commercial exploitation by C-DAC is subject to scheme conditions.

• National-security rationale: The objective is to prevent India from remaining dependent on opaque imported “black-box” technologies in security-critical systems.

• Integrated system: A System-on-Chip (SoC) combines several functions that might otherwise require multiple separate chips onto a single integrated circuit.

• A smartphone SoC, for example, may combine: CPU;

GPU; AI accelerator; memory interfaces; security functions; communication components; and multimedia-processing blocks.

• Why important: SoCs reduce physical size, power consumption and system complexity, making them fundamental to smartphones, IoT devices, automobiles, defence electronics and embedded systems.

• Electronic Design Automation: EDA tools are specialised software platforms used to design, simulate, verify and optimise semiconductor chips.

• A modern chip can contain billions of transistors. It cannot realistically be designed manually. Engineers depend upon EDA software for circuit layout, logic verification, timing analysis, power optimisation and physical design.

• Cost barrier: High-end EDA tools can be very expensive, creating a major barrier for start-ups, universities and small companies.

• Semicon programmes therefore provide shared access to sophisticated design tools so that companies can develop chips without bearing the full infrastructure cost themselves.

• Under the first semiconductor mission, 105 start-ups and MSMEs had already received access to industry-standard EDA tools.

• Shared fabrication: A Multi-Project Wafer (MPW) combines designs from several companies or research groups onto a single semiconductor wafer fabrication run.

• Why useful: Fabricating even a small prototype independently can be extremely expensive.

• By sharing wafer space and manufacturing costs, MPW services allow start-ups and universities to test prototypes at lower cost.

• This is particularly important before a company knows whether its design will work commercially.

• NITI Aayog has also recommended sovereign access to EDA, IP and MPW infrastructure as an important way to lower barriers to semiconductor design.

• Final design stage: Tape-out refers to the point at which a semiconductor design has been completed, verified and prepared for fabrication.

• After tape-out, the design files are sent to the foundry for physical production.

• A successful tape-out does not automatically mean commercial success. The chip still has to be fabricated, packaged, tested, qualified and adopted by customers.

• This explains why Semicon 2.0 introduces a separate deployment incentive after the design stage.

• Seed funding: Eligible start-ups and MSMEs can obtain milestone-linked support of up to ₹15 crore or 50% of project cost, whichever is lower.

• Equity co-investment: The government can invest alongside private venture-capital or private-equity investors. This attempts to mobilise private capital while sharing some of the technological risk.

• Royalty financing: Larger companies can use a royalty-linked model. Under the reported framework, the company repays 5% of product or technology net revenue until the government recovers 1.5 times its financial support.

• Why multiple instruments are needed: Semiconductor design is a high-risk business. Product development can take years, upfront costs are large, and commercial success is uncertain. Traditional bank lending is therefore often unsuitable.

• Diaspora advantage: The commercial-design category permits eligible companies owned and controlled by Overseas Citizens of India, provided the company itself is incorporated and headquartered in India and satisfies the operational requirements.

• Policy rationale: A large number of senior semiconductor engineers, founders and executives of Indian origin have accumulated decades of experience in major international semiconductor companies.

• Allowing OCI-led companies to participate can potentially bring: global product-development experience;

customer relationships; venture capital connections; semiconductor management expertise; and specialised technical know-how

• into Indian-headquartered firms.

• Technology alone is insufficient: Designing a technically successful chip does not guarantee that anyone will buy it.

• Electronics manufacturers prefer proven suppliers because a semiconductor failure can force recalls, damage entire devices and disrupt production.

• A young Indian fabless company may therefore struggle to convince a smartphone maker, automobile supplier or telecom-equipment company to replace a trusted international chip with an unproven domestic alternative.

• Qualification cycles: Semiconductor products often require months or years of testing and certification before large-volume adoption.

• NITI Aayog specifically identifies acceptance of Made-in-India chips as a major challenge because global suppliers have built customer trust over decades.

• Sales-linked support: Eligible semiconductor IP, chips and SoCs introduced under the scheme can receive a reimbursement equivalent to 9% of net sales for five years.

• Ceilings: The reported framework caps the benefit at ₹30 crore per application and ₹120 crore for a company and its group entities across products.

• Policy objective: Unlike a development subsidy, this incentive rewards actual deployment and commercial sales.

• This encourages companies to move beyond designing prototypes towards producing chips that customers use at scale.

• Hidden dependence: Even if India builds semiconductor fabs, those factories can remain critically dependent on imported manufacturing equipment and inputs.

• A semiconductor fab requires: lithography systems;

etching and deposition equipment; metrology tools; high-purity silicon wafers; photomasks; photoresists; specialty chemicals; ultrapure industrial gases; advanced substrates; and testing equipment.

• If these remain entirely imported, domestic fabrication can still be vulnerable to geopolitical restrictions.

• Semicon 2.0 therefore provides support for R&D and production of semiconductor equipment, materials, chemicals and gases.

• Photomask: A photomask contains the pattern corresponding to a semiconductor circuit layer. During lithography, that pattern is transferred onto the wafer.

• Photoresist: Photoresist is a light-sensitive chemical coating placed on the wafer. Exposure to light through a photomask changes the chemical properties of selected regions, allowing circuit patterns to be created.

• These apparently specialised inputs are crucial because semiconductor fabrication involves repeatedly creating extremely precise microscopic patterns.

• Wafer fabrication plant: A semiconductor fab is a highly specialised manufacturing facility where integrated circuits are created on semiconductor wafers.

• Hundreds or even thousands of process steps can be involved.

• A modern fab requires: extreme cleanliness;

uninterrupted high-quality electricity; ultrapure water; highly specialised gases and chemicals; sophisticated manufacturing equipment; process-control expertise; and strong logistics.

• Capital intensity: Fabs are among the most expensive industrial facilities in the world, which explains why governments internationally provide large incentives to attract them.

• Silicon wafer fabs: Conventional integrated-circuit manufacturing based primarily on silicon.

• Compound semiconductor fabs: Use materials formed from combinations of elements, such as gallium nitride or silicon carbide.

• Photonics: Semiconductor technologies interacting with light and optical communication.

• Sensors and MEMS: Devices capable of detecting motion, pressure, temperature and other physical signals.

• Discrete semiconductors: Individual electronic devices such as power transistors and diodes.

• Display fabs: Facilities manufacturing display-related semiconductor technologies.

• Semicon 2.0 therefore avoids treating “semiconductor manufacturing” as one uniform category.

• Silicon Carbide: SiC performs efficiently under high voltage and high temperatures and is increasingly important for EV power electronics, charging infrastructure and renewable-energy systems.

• Gallium Nitride: GaN is valuable for high-frequency and high-power applications, including telecom, radar, power electronics and certain defence systems.

• Strategic opportunity: NITI Aayog argues that India should target areas such as wide-bandgap semiconductors, advanced packaging and selected strategic segments where it can build competitive advantage rather than attempting to reproduce every segment of the global semiconductor industry simultaneously.

• ATMP: Assembly, Testing, Marking and Packaging.

• OSAT: Outsourced Semiconductor Assembly and Test.

• After semiconductor circuits are fabricated on a wafer, individual dies must be separated, packaged, electrically connected and tested before being shipped to electronics manufacturers.

• Why packaging matters: Advanced packaging is no longer merely a low-value final assembly step. Technologies such as chiplets, 2.5D integration, 3D stacking and system-in-package increasingly determine performance.

• Semicon 2.0 therefore treats advanced packaging as a separate strategic pillar.

• Process generation: A semiconductor process node such as 28 nm, 7 nm or 3 nm broadly identifies a generation of chip-manufacturing technology.

• Historically, smaller numbers corresponded more directly to physical transistor dimensions. In modern semiconductor manufacturing, node names are increasingly technology-generation labels rather than exact physical measurements.

• Advanced nodes: Smaller leading-edge nodes are generally associated with higher transistor density and advanced computing applications.

• Mature nodes: Older nodes remain extremely important for automobiles, industrial electronics, power management and embedded systems.

• Semicon 2.0 states that India's research push will move from existing work around 28–110 nm toward more advanced nodes and technologies.

• Semicon 1.0 — ecosystem creation: The first phase concentrated heavily on attracting semiconductor manufacturing investment, fabrication units, packaging and initial domestic design support.

• Semicon 2.0 — ecosystem deepening: The second phase moves much further into:

• indigenous IP;

commercial fabless companies; strategic chips; semiconductor machines; upstream materials; advanced R&D; market deployment; advanced packaging; and specialised talent.

• Incentive design: Manufacturing support is now more differentiated. Secondary reporting on the notified framework indicates 40% central capex support for silicon fabs, while certain compound-semiconductor and packaging categories receive different support levels.

• Policy evolution: This reflects a shift from “bring semiconductor factories to India” towards “build an ecosystem capable of designing, producing, packaging and commercialising semiconductor products”.

• Manufacturing projects: By the Cabinet approval of Semicon 2.0, 12 semiconductor manufacturing projects involving more than ₹1.64 lakh crore of cumulative investment had been approved.

• They included: one silicon fab;

one silicon carbide fab; one integrated GaN Micro LED display fab; and nine packaging facilities.

• Commercial production: The government reported that Micron, Kaynes and CG Semi had begun commercial production, with additional facilities expected to follow.

• Design: Twenty-four semiconductor-design projects from start-ups and MSMEs had received financial support, while 105 start-ups/MSMEs had received access to EDA tools.

• High import dependence: NITI Aayog estimates that 90–95% of India's current semiconductor demand is met through imports.

• Supply concentration: The global semiconductor chain is concentrated across a relatively small number of countries and companies.

• This creates vulnerability to: geopolitical tensions;

natural disasters; export controls; trade restrictions; wars; shipping disruptions; and technology-denial regimes.

• The global chip shortage during the COVID-19 period demonstrated how semiconductor shortages can interrupt automobile and electronics production even thousands of kilometres away from chip-manufacturing centres.

• Talent base: India already has a very large engineering workforce employed in semiconductor design.

• Lower capital intensity: Fabless semiconductor companies require much less capital than advanced fabrication plants.

• Software-design overlap: India's established strength in software, embedded systems and electronics engineering can complement chip-design activities.

• Large domestic market: India can potentially provide early demand in telecommunications, automobiles, smart meters, defence, industrial electronics and consumer products.

• Strategic opportunity: Designing Indian products for Indian requirements can create intellectual property that can later be exported globally.

• Beyond engineers alone: Semiconductor manufacturing requires several categories of skilled workers:

• chip-design engineers;

process engineers; packaging specialists; materials scientists; clean-room technicians; equipment engineers; construction specialists; and system architects.

• Government progress: The government says its earlier target of developing 85,000 semiconductor engineers was reached within four years, and a new target of training one lakh more engineers has been announced.

• Academic infrastructure: EDA-based semiconductor training has been extended across hundreds of academic institutions, while students from Tier-II and Tier-III institutions have also designed chips.

• The challenge now is shifting from broad training numbers towards specialised, production-ready expertise.

• Nodal agency: The India Semiconductor Mission (ISM), under the Ministry of Electronics and Information Technology, is the nodal agency for implementing Semicon 2.0.

• Its functions include: inviting applications;

technical appraisal; financial appraisal; recommending projects; monitoring implementation; and facilitating incentive disbursement.

• ISM can use C-DAC for implementing certain design and deployment categories.

• Review mechanism: A mid-term assessment is planned after three years, allowing the government to modify the programme if technological or market conditions change.

• Trusted hardware: A defence or critical-infrastructure system may be vulnerable if its essential chips are sourced entirely from external suppliers whose designs and manufacturing processes India cannot independently verify.

• Supply denial: Export controls can restrict access to critical technologies during geopolitical disputes.

• Replacement risk: A foreign component may become unavailable even after it is integrated into an aircraft, radar system, power grid or telecom network.

• Technological sovereignty: Indigenous design allows India to understand and control critical architectures and reduce dependence on “black-box” components.

• NITI Aayog explicitly identifies imported chips in aerospace, UAVs, naval systems and other defence platforms as a national-security vulnerability.

• Compute dependence: Modern AI systems depend heavily on accelerators such as GPUs, AI chips and high-bandwidth memory.

• Edge AI: Increasingly, AI inference is also performed locally on phones, vehicles, drones and industrial devices.

• Strategic consequence: A country seeking leadership in artificial intelligence but remaining dependent on foreign computing hardware faces technological vulnerability.

• Therefore semiconductor capability, cloud computing, AI research and digital infrastructure are increasingly interconnected elements of technological sovereignty.

• Capital intensity: Semiconductor projects require very large long-term investment and may take years before generating returns.

• Technology gap: Leading-edge semiconductor fabrication and equipment are controlled by a small number of specialised global companies.

• Customer trust: New Indian chips must establish reliability before global electronics manufacturers will adopt them.

• Weak domestic IP base: India possesses engineers but comparatively fewer large Indian-owned semiconductor product companies.

• Equipment dependence: Much critical semiconductor equipment remains concentrated among foreign suppliers.

• Materials ecosystem: High-purity chemicals, gases, substrates and specialty materials require dedicated domestic supply chains.

• Infrastructure: Fabs need extremely reliable electricity, ultrapure water, logistics and clean-room infrastructure.

• Talent depth: Large numbers of engineers alone cannot replace decades of experience in yield optimisation, process integration and semiconductor production management.

• Fast technology cycles: A fab or chip design can become technologically outdated before investment costs have been fully recovered.

• Global competition: The United States, European Union, Japan, South Korea, Taiwan and China are themselves spending heavily to secure semiconductor supply chains.

• Post-pandemic industrial policy: The COVID-era chip shortage demonstrated that concentrated supply chains can disrupt automobile, electronics and defence manufacturing worldwide.

• Geopolitical competition: Semiconductor export controls have become an important instrument of technology competition, particularly between the United States and China.

• Friend-shoring: Governments and companies increasingly seek geographically diversified and politically trusted semiconductor supply chains.

• India's opportunity: India offers:

• large domestic demand;

a large engineering workforce; geopolitical partnerships; growing electronics manufacturing; and government incentives.

• However, India must demonstrate high yields, manufacturing reliability, global quality and policy stability before it becomes indispensable to the global semiconductor chain.

• 2035 strategy: NITI Aayog's May 2026 report argues that India should not try to reproduce the entire semiconductor ecosystem simultaneously. Instead, it should concentrate on segments where India can build differentiated global strength.

• The roadmap stresses: strategic semiconductor IP;

sovereign access to EDA and MPW infrastructure; advanced packaging; compound semiconductors; trusted mission-critical manufacturing; materials and substrates; talent development; and global partnerships.

• Core philosophy: The report argues that India should aim to become “indispensable” in selected global value-chain segments rather than merely imitate established semiconductor powers.

• Semicon 2.0 substantially reflects this broader ecosystem approach.

• Science and Technology: Semiconductor technology, chip fabrication, SoCs, EDA, compound semiconductors, MEMS and advanced packaging.

• Economy: Industrial policy, manufacturing, capital subsidies, start-up financing and import dependence.

• National Security: Trusted electronics, strategic chips, defence supply chains and technological sovereignty.

• International Relations: Global technology competition, supply-chain diversification and strategic technology partnerships.

• Governance: Mission-mode implementation, government-private sector cooperation and industrial-policy design.

• For GS3, Semicon 2.0 is an excellent example of how science and technology, economic policy, national security and strategic autonomy increasingly overlap.

• Prioritise Indian IP creation: Incentives should ultimately be judged by whether India creates globally competitive Indian-owned semiconductor intellectual property, not simply by the number of subsidised projects.

• Move from design to deployment: Government procurement, industry partnerships and transparent qualification mechanisms can help credible Indian chips overcome the first-customer barrier.

• Create patient deep-tech capital: Semiconductor start-ups require longer investment horizons than conventional software companies. Equity co-investment and specialised semiconductor funds can address this financing gap.

• Build upstream industries: India must simultaneously develop wafers, substrates, photomasks, specialty gases, chemicals and precision semiconductor equipment.

• Strengthen R&D: Universities, national laboratories and industry should collaborate on compound semiconductors, photonics, chiplets, advanced packaging, AI accelerators and next-generation materials.

• Develop specialised talent: Training should move beyond numbers towards fab-ready technicians, process engineers, materials scientists, packaging engineers and system architects.

• Use the Indian market strategically: Telecom, defence, automobiles, smart meters, power electronics and public digital infrastructure can provide early demand for trusted domestic chips where performance standards are met.

• Maintain technology partnerships: Semiconductor self-reliance should not mean technological isolation. India should deepen partnerships with trusted global firms and countries while simultaneously developing domestic capabilities.

• Create semiconductor clusters: Fabs, packaging units, suppliers, design companies, logistics and research institutions should be geographically integrated to generate economies of scale.

• Ensure policy stability: Semiconductor investments have long gestation periods. Stable incentives, predictable taxation, faster approvals and long-term regulatory certainty are therefore essential.

• Measure outcomes rather than approvals: Success should be assessed through commercial chip deployments, Indian-owned patents, export revenues, manufacturing yield, domestic value addition and global market share—not only through announced investment.